Altera, an Intel Company, disclosed various FPGA hardware, software, and developmental tools that simplify accessibility across a broad range of use cases. During its annual developer’s conference, Altera discussed new information on its next-generation, power- and cost-optimized Agilex 3 FPGAs and revealed new development kits and software support for its Agilex 5 FPGAs.
A thorough FPGA portfolio delivers flexible hardware that is adaptable for changing industry needs in intelligent computing. Agilex FPGAs are embedded with AI Tensor Blocks and the Altera FPGA AI Suite, which accelerates FPGA development utilizing general frameworks such as TensorFlow, PyTorch, and OpenVINO toolkit.
Agilex 3 FPGAs leverage an on-chip dual Cortex A55 ARM hard processor subsystem with a programmable fabric infused with AI capabilities with density ranging from 25K-135K logic elements. It supports real-time compute for time-sensitive applications such as autonomous vehicles and industrial Internet of Things (IIoT). Integrating sensors, drivers, actuators, and machine learning algorithms is simplified with the platform.
For securing critical applications, Agilex 3 FPGAs add numerous security improvements over the previous generation, including bitstream encryption, authentication, and physical anti-tamper detection. Included is Altera’s HyperFlex architecture, providing a 1.9X performance improvement over prior generation. Integrated high-speed transceivers operating up to 12.5Gbps and support for LPDDR4 memory are also included.Altera announced the newest features offered in its Quartus Prime Pro 24.3 software, unlocking more devices within the Agilex family and facilitates enhanced support for embedded applications.
Customers can use this upcoming release to start designing Agilex 5 FPGA D-series, which target an even broader range of use cases compared to Agilex 5 FPGA E-series, which are optimized to deliver efficient compute in edge applications. The release also supports applications that employ either an integrated hard-processor subsystem or Altera’s RISC-V solution, the Nios V soft-core processor that can be instantiated in the FPGA fabric.
Users can now access Agilex 5 FPGA design models that feature Nios V capabilities such as lockstep, full ECC, and branch prediction. New OS and RTOS support for the Agilex 5 SoC FPGA-based hard processor subsystem is included in the latest releases of Linux, VxWorks, and Zephyr.
